1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device including an array of electrically erasable programmable non-volatile memory cells.
2. Description of the Related Art
Conventionally known non-volatile semiconductor memory devices include NOR-type flash memories and NAND-type flash memories. In such the flash memories, a memory cell is selected when a row decoder selects a word line. The row decoder may be configured as proposed variously (see JP 2000-49312A, for example).
In the conventional flash memories, the row decoder has a larger size, which causes interference with downsizing the flash memories. Particularly, in the NOR-type flash memory, while a non-selected word line is brought into a floating state, capacitive coupling thereof with other word lines elevates the potential on the non-selected word line, which may cause failed read. Therefore, the row decoder also inevitably requires a configuration to prevent this problem though such the configuration increases the number of elements and the number of wires correspondingly, which may cause interference with downsizing.